In the fabrication of modern semiconductor devices, the ever increasing device density and decreasing device dimensions demand more stringent requirements in the packaging or interconnecting techniques of the devices. In recent years, a flip-chip attachment method or flip-chip direct chip attachment (DCA) method has been used in packaging integrated circuit chips. In the flip-chip attachment method, instead of attaching an integrated circuit lead frame in a package, an array of solder balls is formed on the surface of the die for the subsequent bonding to a printed circuit board or an interposer. The formation of the solder balls can be carried out by an evaporation method utilizing a solder material consisting mainly of tin and lead through a mask to produce the balls in a desired pattern. More recently, the techniques of electrodeposition or printing have been used to mass produce solder balls in a flip-chip packaging process.
In the direct chip attachment method, all the interconnections between a semiconductor chip and a printed circuit board (PCB) or a flexible substrate can be formed simultaneously and therefore maximizing fabrication throughputs. For instance, in direct attachment, solder bumps or solder balls are used to connect a chip directly to a printed circuit board or a flexible substrate. In a regular printed circuit board, the density of the interconnections is not formed high enough to match that normally found on a chip surface. In other words, the pitch between the bond pads formed on a chip is smaller than the pitch formed between interconnections on a printed circuit board. An interposer is therefore used to provide a transition and to accommodate the bond pads/interconnections which are spaced differently. An interposer board is frequently fabricated of the same material as that used in the printed circuit board, i.e., an epoxy-type polymeric material. When a high density interconnect printed circuit board is utilized in a flip-chip method for bonding to a semiconductor chip, the use of the interposer may not be necessary.
The use of organic substrates, or polymeric-base substrates, in printed circuit boards, flexible substrates or interposers introduces a new source of problem for the flip-chip bonding of a silicon chip which is mostly inorganic to such substrates. The problem is the mismatch of coefficients of thermal expansion (CTE) between the printed circuit board and the silicon chip. The coefficient of thermal expansion for the printed circuit board material is at least five times that of the silicon material. The extreme mismatch in CTE's between the silicon chip and the organic substrate of the printed circuit board therefore subjects solder joints formed therein between to extremely large thermal strains, which leads to premature failure of the solder connections.
One method proposed for alleviating such thermal strains is the introduction of an encapsulating layer between the silicon chip and the organic substrate. The encapsulating material, known as an underfill, which is typically a silica filled epoxy is used to fill the gap (or standoff) between the printed circuit board and the silicon chip. Since the silicon chip is normally covered, in a final fabrication step, by a polymer passivation/stress buffer layer such as a polyimide film, the underfill forms a bond between the polyimide layer on the chip and the organic substrate of the printed circuit board encapsulating the solder joints.
Referring initially to FIG. 1, wherein a flip-chip 10 bonded by a plurality of solder balls 12 and an underfill layer 14 is shown. The encapsulating material, or the underfill layer 14, is typically a silica filled epoxy for filling the gap, or the standoff, between the printed circuit board 16 and the silicon chip 18. As shown in FIG. 1, the underfill layer 14 forms a bond between a polyimide layer 20, which is a passivation/stress buffer layer that covers the silicon chip 18, and the printed circuit board 16 encapsulating the solder balls 12.
While the introduction of the underfill layer between a silicon chip and an organic substrate for the printed circuit board has enhanced the thermal cycling resistance of a flip chip assembly, the dispensing of the underfill material in between a silicon chip and a substrate and filling the gap is a time consuming task. In one conventional method, as shown in FIGS. 2A˜2C, an underfill dispenser 22 is first used to dispense an underfill material 24 onto the top surface 26 of a substrate 28. A layer 30 of the underfill material 24 is thus formed on the top surface 26. A chip holder 32, usually a vacuum holder, is then used to position an IC chip 34 which is pre-deposited with a plurality of solder balls 36 on a top surface 38 over the substrate 28. The IC chip, or die 34 is then pressed onto the substrate 28 with the plurality of solder balls 36 connecting to corresponding electrical conductors (not shown) on the surface 26 of the substrate 28. The assembly 40 for the flip chip is then placed in a reflow oven and heated to a temperature not less than the reflow temperature for the solder material utilized in the plurality of solder balls 36. The reflow process further cures the underfill material 30 and improves its mechanical strength.
Several drawbacks are inherent in this technique. For instance, there is possibly an underfill material layer between the plurality of the solder balls on the IC chip and the plurality of electrical conductors on the substrate. Since the underfill material is an insulating material, this affects the contact resistance formed between the joints. Secondly, in the process of pressing the IC die 34 onto the underfill material layer 30, air entrapment in the underfill material 30 is inevitable. Trapped air bubbles in the underfill material layer 30, or in the epoxy material layer 30, affect the mechanical strength enhancement by the underfill material and furthermore, affect the adhesion formed between the underfill material and the IC die or the substrate.
In another conventional technique for dispensing underfill materials, shown in FIGS. 3A˜3F, an underfill material is fed into the standoff between an IC die and a substrate by the capillary effect on the underfill liquid. As shown in FIG. 3A, a wafer 42 is first sectioned into individual dies 44 by a diamond saw 46. The IC dies 44 are provided with a plurality of solder balls 48 on a top surface 50 of the dies. After all the dies 44 are severed from wafer 42, they are placed in a holder tray 52, as shown in FIG. 3B. In the next step of the process, a vacuum head 54 is used to remove an IC die 44 from the tray 52 and to position the die over a substrate 56. It is noted that a plurality of electrical conductors 58, corresponding to the number and positions of the solder balls 48 are provided on a top surface 60 of the substrate 56. It should be noted that the substrate 56 may be either a printed circuit board or an interposer. After the IC die 44 is mounted to substrate 56 by intimately contacting the solder balls 48 with the electrical conductors 58, as shown in FIG. 3D, a solder reflow process is carried out to reflow the solder and to form a permanent bond between the IC die 44 and the substrate 56. It should be noted that the plurality of electrical conductors 58 are not shown in FIG. 3D for simplicity reasons.
The flip chip package 62 is then ready for the underfill process in which an underfill dispenser 64, such as a liquid syringe, is used to dispense an underfill material 66 at an edge of the flip chip package 62. Since a gap 68, or the standoff, between the chip 44 and the substrate 56 is relatively small, i.e., in the neighborhood between about 50 μm and about 100 μm, a capillary effect causes the underfill material 66 to flow into the gap 68 and fill up the gap. Since the underfill dispensing process utilizes capillary effect, several factors may influence the underfill filling process. For instance, the viscosity of the underfill materials 56 and the temperature of the substrate 56 and the IC die 44. Moreover, the capillary flow process for the underfill material 56 is time consuming, i.e., up to 1 minute flow time required to fill under an IC die which has a dimension of 10 mm×10 mm. A completed flip chip 62 with the underfill dispensed between the IC die 44 and the substrate 56 is shown in FIG. 3F.
In still another conventional technique in bonding an IC chip to a substrate, non-conducting adhesives have been used to achieve the bonding. This is shown in FIGS. 4A and 4B. An assembly 70 is formed by an IC chip 72 and a substrate 74 bonded together by a non-conductive adhesive 76. Electrical communication between the IC chips 72 and the substrate 74 is established between bond pads 78 on the IC chip 72 and the bond pads 80 on the substrate 74 with gold bumps 82. A serious thermal mismatch occurs between the non-conductive adhesive 76, the silicon chip 72, and the polymeric-based substrate 74. After the bonding process by the non-conductive adhesive 76, the assembly 70 may bow or warp due to built-in thermal stresses. This is shown in FIG. 4B. An IC chip/substrate assembly 70 bonded together with a non-conductive adhesive 76 without containing any fillers in the adhesive cannot pass a thermal stress test or any other thermal reliability test. A failed sample of the IC chip/substrate assembly after a thermal stress test, i.e., was cycled between −55° C. and 125° C., is shown in FIG. 5 in an electronic scanning micrograph.
In a copending application assigned to the common assignee of the present invention, attorney Docket No. 64600-085, a method for bonding an IC chip to a substrate by a non-conductive adhesive containing between about 5% and 25% of a non-conductive filler and an IC chip/substrate assembly bonded together by the method are disclosed. As shown in FIGS. 6A-6D, in the first step of the process, a substrate 90 that has bond pads 84 formed on a top surface 86 is provided. A non-conductive adhesive 88 is then deposited on a top surface 86 to cover the bond pads 84. The non-conductive adhesive contains a non-conductive filler such as silica sand having particle sizes between about 0.2 μm and about 20 μm. An IC chip 94 that has a plurality of bumps 96 formed on an active surface 98 is then positioned on top of the substrate 90. The plurality of bumps may be suitably formed of a metallic material that has a significantly lower hardness when compared to the hardness of the non-conductive filler particles, such that the filler particles are pressed into the top surface of the bumps 96 and not to impede electrical communication between the bumps 96 and the bond pads 84.
In the next step of the process, as shown in FIG. 6C, an inner-lead bonder 110 is used to bond the IC chip 94 and the substrate 90 together under suitable heat and pressure forming an IC chip/substrate assembly 100. FIG. 6D shows the assembly 100 after the bonding process is completed in the inner-lead bonder 110.
The process described in the co-pending application, while reduces the mismatch in the coefficients of thermal expansion between the IC chip and the substrate to certain extent, does not provide sufficient reduction in such mismatch in many circumstances. In other words, the deformation shown in FIG. 4B is still observed when such non-conductive fillers are used in the underfill, i.e., the non-conductive adhesive material.
It is therefore an object of the present invention to provide a method for bonding an IC chip to a substrate by a non-conductive adhesive without the drawbacks or shortcomings of the conventional bonding methods.
It is another object of the present invention to provide a method for bonding an IC chip to a substrate by a non-conductive adhesive wherein only a minimal amount of the non-conductive adhesive is required, thus minimizing the thermal mismatch.
It is a further object of the present invention to provide a method for bonding an IC chip to a substrate by a non-conductive adhesive by forming dummy bumps on at least one of the bonding surfaces of the IC chip and the substrate.
It is another further object of the present invention to provide a method for bonding an IC chip to a substrate by a non-conductive adhesive by forming dummy bumps on both bonding surfaces of the IC chip and the substrate.
It is still another object of the present invention to provide an IC chip/substrate assembly bonded together by a non-conductive adhesive wherein dummy bumps are formed on the bonding surface of at least one of the IC chip and the substrate.
It is still another further object of the present invention to provide an IC chip/substrate assembly bonded together by a non-conductive adhesive in which dummy bumps are formed on the bonding surfaces of both the IC chip and the substrate.